Dibutyryl cAMP inhibits endotoxin-induced increases in pulmonary vascular resistance and fluid filtration coefficient in the perfused rat lung

We investigated the effects of pre-treatment with dibutyryl cAMP (db-cAMP) or cGMP on endotoxin-induced hemodynamic changes and pulmonary vascular permeability in isolated perfused rat lungs. Intraperitoneal injection of Salmonella enteritidis endotoxin (2 mg/kg) caused increases in pulmonary arterial resistance (Ra) after venous reservoir elevation, in pulmonary filtration coefficient (Kf) and in lung wet-to-dry (W/D) weight ratio. Pre-treatment with db-cAMP blocked endotoxin-induced increases in Ra, Kf and W/D weight ratio. Pre-treatment with cGMP attenuated only the increase in Ra caused by endotoxin. Moreover, administration of db-cAMP 2 hours after endotoxin injection attenuated the increase in Ra induced by endotoxin treatment. The increases in Kf and W/D weight ratio caused by endotoxin were not affected by post-treatment with db-cAMP. Since the increases in Ra, Kf and W/D weight ratio caused by endotoxin were blocked by pre-treatment with db-cAMP, agents that increase intracellular cAMP level may be useful to prevent acute pulmonary vascular injury.     

Multiple-symbol parallel decoding for variable length codes

In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redundant number of codeword lengths from which incorrect values are removed by recursive selection. Next, the index for each symbol corresponding the detected codeword is generated from the length determining the page and the partial codeword defining the offset in symbol table. The symbol lookup can be performed independently from symbol table. Finally, the sum of the valid codeword lengths is provided to an external shifter aligning the encoded input stream for a new decoding cycle. In order to prove feasibility and determine the limiting factors of our proposal, the variable length decoder has been implemented on an field-programmable gate-array (FPGA) technology. When applied to MPEG-2 standard benchmark scenes, on average 4.8 codewords are decoded per cycle resulting in the throughput of 106 million symbols per second.     

A Low-Power Multithreaded Processor for Software Defined Radio

Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications. Michael Schulte received a B.S. degree in Electrical Engineering from the University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless systems. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing. John Glossner is CTO & Executive Vice President at Sandbridge Technologies. Prior to co-founding Sandbridge, John managed the Advanced DSP Technology group, Broadband Transmission Systems group, and was Access Aggregation Business Development manager at IBM’s T.J. Watson Research Center. Prior to IBM, John managed the software effort in Lucent/Motorola’s Starcore DSP design center. John received a Ph.D. in Computer Architecture from TU Delft in the Netherlands for his work on a Multithreaded Java processor with DSP capability. He also received an M.S. degree in Engineering Management and an M.S.E.E. from NTU. John also holds a B.S.E.E. degree from Penn State. John has more than 60 publications and 12 issued patents. Dr. Sanjay Jinturkar is the Director of Software at Sandbridge and manages the systems software and communications software groups. Previously, he managed the software tools group at StarCore. He has a Ph.D in Computer Science from University of Virginia and holds 20 publications and 4 patents. Mayan Moudgill obtained a Ph.D. in Computer Science from Cornell University in 1994, after which he joined IBM at the Thomas J. Watson Research Center. He worked on a variety of computer architecture and compiler related projects, including the VLIW research compiler, Linux ports for the 40x series embedded processors and simulators for the Power 4. In 2001, he co-founded Sandbridge Technologies, a start-up that is developing digital signal processors targeted at 3G wireless phones. Suman Mamidi is a graduate student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He received his M.S. degree from the University of Wisconsin-Madison in December, 2003 and is currently working towards his PhD. His research interests include low-power processors, hardware accelerators, multithreaded processors, reconfigurable hardware, and embedded systems. Stamatis Vassiliadis was born in Manolates, Samos, Greece, in 1951. He is currently a Chair Professor in the Electrical Engineering, Mathematics, and Computer Science (EEMCS) department of Delft University of Technology (TU Delft), The Netherlands. He previously served in the Electrical and Computer Engineering faculties of Cornell University, Ithaca, NY and the State University of New York (S.U.N.Y.), Binghamton, NY. For a decade, he worked with IBM, where he was involved in a number of advanced research and development projects. He received numerous awards for his work, including 24 publication awards, 15 invention awards, and an outstanding innovation award for engineering/scientific hardware design. His 73 USA patents rank him as the top all time IBM inventor. Dr. Vassiliadis is an ACM fellow, an IEEE fellow and a member of the Royal Netherlands Academy of Arts and Sciences (KNAW).     

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.Mihai Sima was born in Bucharest, Romania. He received the MS degree in Electrical Engineering from Politehnica University of Bucharest, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had been with the Microelectronics Company in Bucharest for 3 years, where he was involved in instrumentation electronics for integrated circuit testing. Subsequently, he joined the Telecommunications Department of Politehnica University of Bucharest, where he had been involved in digital signal processing and speech recognition for 6 years. More recently, he had been with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, where he worked on reconfigurable architectures for mediaprocessing domain. He is currently an assistant professor with the Department of Electrical and Computer Engineering, University of Victoria, B.C., Canada. His research interests include computer architecture, reconfigurable computing, embedded systems, digital signal processing, and speech recognition.Sorin D. Coofan was born in Mizil, Romania. He received the MS degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He had worked with the Research & Development Institute for Electronic Components (ICCE) in Bucharest for a decade, being involved in structured design of digital systems, design rule checking of ICs layout, logic and mixed-mode simulation of electronic circuits, testability analysis, and image processing. He is currently an associate professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, reconfigurable computing, nano-electronics, neural networks, computational geometry, and computer aided design.Jos T.J. van Eijndhoven was born in Roosendaal, The Netherlands. He studied Electrical Engineering at the Eindhoven University of Technology, The Netherlands, obtaining the M.Sc. and Ph.D. degrees in 1981 and 1984, respectively, for a work on piecewise linear circuit simulation. Then, he became a senior research member in the design automation group of the Eindhoven University of Technology. In 1986 he spent a sabbatical period at the IBM Thomas J. Watson Research Laboratory, Yorktown Heights, New York, for research on high level synthesis. In 1998 he joined Philips Research Laboratories in Eindhoven, The Netherlands, to work on the architectural design of programmable multimedia hardware and the associated mapping of media processing applications.Stamatis Vassiliadis was born in Manolates, Samos, Greece. He is a professor with the Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft University of Technology, The Netherlands. He has also served in the faculties of Cornell University, Ithaca, NY, and the State University of New York (S.U.N.Y.), Binghamton, NY.He hadworked for a decade with IBM in the AdvancedWorkstations and Systems laboratory in Austin TX, the Mid-Hudson Valley Laboratory in Poughkeepsie, NY, and the Glendale Laboratory in Endicott, NY. In IBM he was involved in a number of projects regarding computer design, organizations, and architectures and the leadership to advanced research projects. A number of his design and implementation proposals have been implemented in commerciallyavailable systems and processors including the IBM 9370 model 60 computer system, the IBM POWER II, the IBM AS/400 Models 400, 500, and 510, Server Models 40S and 50S, the IBM AS/400 Advanced 36, and the IBM S/390 G4 and G5 computer systems. For his work, he received numerous awards including 23 levels of Publication Achievement Awards, 15 levels of Invention Achievement Awards and an Outstanding Innovation Award for Engineering/Scientific Hardware Design in 1989. In 1990 he has been awarded the highest number of USA patents in IBM, six of his 70 USA patents being rated with the highest patent ranking in IBM.Kees A. Vissers graduated the Delft University of Technology, receiving his M.Sc. in 1980. He started directly with Philips Research Laboratories in Eindhoven where he was involved in highlevel simulation and high-level synthesis. He had been heading the research on hardware/software co-design and system level design for many years, and had a significant contribution to the TriMedia VLIW processor. From 1987 till 1988 he was a visiting researcher at Carnegie Mellon University, Pittsburgh, Pennsylvania, with the group of Don Thomas. He is currently a Research Fellow with University of California at Berkeley, Department of Electrical Engineering and Computer Sciences. His research interests include video processing, embedded media processing systems, and reconfigurable computing.     

Characterization of ligand-functionalized microcantilevers for metal ion sensing

A sensor for metal cations is demonstrated using single and binary mixtures of different thiolated ligands as self-assembled monolayers (SAMs) functionalized on silicon microcantilevers (MCs) with gold nanostructured surfaces. Binding of charged metal ions to the active surface of a cantilever induces an apparent surface stress, thereby causing static bending of the MC that is detected in this work by a beam-bending technique. A MC response mechanism based on changes in surface charge is discussed. The monodentated ligands arranged as SAMs on the MC surface are not expected to fully satisfy the coordination sphere of the detected metals. This leads to lower binding constants than would be expected for chelating ligands, but reversible responses. The modest binding constants are compensated in terms of the magnitudes of responses by the inherent higher sensitivity of the nanostructured approach as opposed to more traditional smooth surface MCs. Response characteristics are optimized in terms of SAM formation time, concentration of ligand solution, and pH of working buffer solution. Limits of detection for the tested mono-, di-, and trivalent metal ions are in low to submicromolar range. The results indicated that shapes and magnitudes of response profiles are characteristics of the metal ions and type of SAM. The response factors for a given SAM with the tested metal ions, or for a given metal with the tested SAMs, varied by roughly 1 order of magnitude. While the observed selectivity is not large, it is anticipated that sufficient ionic recognition contrast is available for selective metal ion identification when differentially functionalized arrays of MCs (different ligands on different cantilevers in the array) are used in conjunction with pattern recognition techniques.     

Inequality path constraints in optimal control: a finite iteration -convergent scheme based on pointwise discretization

This paper presents a new result in the analysis and implementation of path constraints in optimal control problems (OCPs). The scheme uses the well-known concept of discretizing path constraints on a finite number of points, yielding a set of interior-time point constraints replacing the original path constraints. The approach replaces the original OCP by a sequence of OCPs which is shown to converge in a finite number of steps to the solution of the original path constrained problem with -accuracy. Numerical results, verifying the theoretical analysis, are presented. The method is shown to be effective and promising for future applications, particularly in control vector parameterization implementations.     

High-bandwidth Address Generation Unit

In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 − bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

Instruction-Level Fault Tolerance Configurability

Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance (FT) is becoming increasingly important in computing systems. Several schemes have been proposed to enable a user to configure the FT at the application level, thereby enabling the user to trade stronger FT for performance or vice versa. In this paper, we propose supporting instruction-level rather than application-level configurability of FT, since different parts of some applications (e.g., multimedia) can have different reliability requirements. Weak or no FT will be applied to less critical parts, resulting in time and/or resource gains. These gains can be used to apply stronger FT techniques to the more critical parts; hence increasing the overall reliability. The paper shows how some existing FT techniques can be adapted to support instruction-level FT configurability, how a programmer can specify the desired FT level of the instructions, and how the compiler can manage it automatically. A comparison between the existing FT scheme EDDI (which duplicates all instructions) and the proposed approach is performed both at the kernel and at full application levels. The simulation results show that both the performance and the energy consumption are significantly improved (up to 50% at the kernel and up to 16% at full application level), while the fault coverage depends on the application. For the full application (JPEG encoder), our approach is only applied to one kernel in order to avoid increasing the programming effort significantly.

An improved method for the hot strip mill production scheduling problem

In most research on the hot strip mill production scheduling problem (HSMPSP) arising in the steel industry, it is accepted that a schedule with lower penalty caused by jumps of width, hardness, and gauge will result in lower roller wear, so it is regarded as a better schedule. However, based on the analysis of production processes, it is realised that rolling each coil also cause roller wear. In order to assessing the roller wear associated with production scheduling more precisely, it is necessary to consider it as another factor besides those jumps, especially when complicated constraints are involved. In this paper, an improved method is proposed to quantify the expected wear of the rollers done by those jumps and rolling processes. Then the HSMPSP whose objective is to maximise the total length of all scheduled coils is formulated as a team orienteering problem with time windows and additional production constraints. A heuristic method combining an improved Ant Colony Extended algorithm with local search procedures dedicated to HSMPSP is developed. Finally, computational results on instances generated based on production data from an integrated steel mill in China indicate that the proposed algorithm is a promising solution specific to HSMPSP.     

Shear crack growth in brittle materials modeled by constrained Cosserat elasticity

The propagation of in-plane shear cracks is investigated in brittle microstructured materials modeled by the constrained Cosserat elasticity. This theory introduces characteristic material lengths in order to describe the scale effects that emerge from the underlying microstructure and has proved to be very effective for modeling complex microstructured materials. An exact solution is obtained based on integral transforms and the Wiener-Hopf technique. Numerical results are presented illustrating the dependence of the stress intensity factor and the energy release rate upon the loading profile, the propagation velocity, and the characteristic material lengths of Cosserat elasticity. It is shown that depending on the Cosserat microstructural lengths the limiting crack propagation velocity can be significantly lower than the classical Rayleigh limit. Moreover, strengthening effects are observed when the characteristic material lengths become comparable to the geometrical lengths of the problem, a behavior that has been experimentally verified in fracture of ceramics.